1. Field of the Invention
The present invention generally relates to structure and process for multi-layer thin film wiring structures and, more particularly, to the fabrication of multi-layer thin film structures in a non-serial manner by creating testable sub-units and then joining them together to form a finished three-dimensional wiring matrix.
2. Description of the Prior Art
Fabrication of multi-layer thin film interconnect structures for high-density integrated circuits generally involves the sequential build up of metal-patterned dielectric layers on silicon or ceramic substrates. Among the various dielectric/insulator materials in thin film structures, sputtered (or PECVD) quartz, silicon nitride, and high-temperature stable polymers, especially polyimides, are most commonly used in conjunction with high-conductivity metallurgy such as aluminum/copper, gold, and/or copper.
The approach based on sequential building of each layer to form high-density wiring structures, however, suffers from the problem that every time a new layer is fabricated, the previously built layers are exposed to the entire process excursions including thermal, chemical solvents, mechanical and other stress-related operations. In addition, since the electrical performance and long-term reliability of the sequentially built structure can only be determined after the conclusion of the entire fabrication process, the finished part may have to be discarded if the performance does not meet the required specifications. This results in high cost of production and has other obvious limitations in terms of cycle time and throughput.
When using polyimide dielectric (or other high-temperature polymers), an alternate approach to thin film interconnect structures is based on the assembly of individual electrically testable metallized thin films (layers) which are laminated at high temperature such that metal-to-metal and polymer-to-polymer bonding can be achieved. This method eliminates some of the limitations of the sequential process, as each metallized dielectric layer is fabricated as a single unit which can be fully tested for the desired electrical characteristics, then multiple layers are stacked and laminated under heat and pressure. Although this method would be potentially superior to the sequential build up of layers, it has a fundamental problem with regard to the dimensional stability of the structure during both individual layer build and during the joining of the individual layers to form the composite structure. This is due to the fact that the thin polyimide films are generally fragile and flexible and are subject to deformation under thermal or solvent-related stress conditions. This can result in pattern misalignment and distortion during layer fabrication or in the process of lamination and also when the composite structure undergoes accelerated reliability tests involving temperature and humidity excursions.
Japanese Patent No. J63-274199 (Application No. (1987) 62-108987) discloses a "Multilayer Wiring Formation Method" involving the build up of individual layers comprising polyimide insulator with copper wiring and copper/gold interface metal. This method is based on metal patterning of partially cured polyimide layers formed on a substrate, after which the layers are peeled off from the substrate, smoothed by vacuum, stacked, and then laminated in one step by heating under pressure. During this process, interlayer bonding occurs due to polymer interdiffusion at the interface which is also accompanied by full polymer cure, and at the same time gold/gold joining causes metal interconnections. However, this process suffers from the limitations of potential pattern misalignment and distortion, as mentioned above.
The following U.S. patents relate generally to methods of forming metallurgical patterns in insulator films:
U.S. Pat. No. 2,692,190 to Pritikin is concerned with a method for generating embedded metallurgy to fabricate printed circuits having large dimensions on a temporary base plate which is removed by chemical etching. After the conductor pattern is defined and an insulator, such as Teflon.RTM., polystyrene, etc., is applied, the base plate is removed by a selective etching process.
U.S. Pat. No. 3,181,986 to Pritikin also relates to printed circuits with the difference from the above patent being that the temporary base plate is not consumed and thus the process is less expensive.
U.S. Pat. No. 3,466,206 to Beck relates to embedded printed circuits having integral aligned through terminals exposed on both sides by a substractive etch process. The metal sheet is copper, silver, gold, brass, stainless steel, etc., and the insulator is a thermosetting or cold-setting resin, self-hardening resin or one which requires heat and pressure to cure, including epoxies, phenolics, melamine, Teflon, or composites with glass fillers.
U.S. Pat. No. 3,541,222 to Parks et al. is concerned with a connector screen or "interposer" comprising conductive connector elements embedded in a deformable insulator such that the conductive elements are protruding from both sides.
U.S. Pat. No. 4,604,160 to Murakami et al. relates to a method for fabricating a flexible printed wiring board with emphasis on the adhesion of the plating resist and the conductor pattern during the plating process.
U.S. Pat. No. 4,707,657 to Boegh-Petersen is concerned with double-sided printed circuit boards of a connector assembly, thin film and thick film circuit board, and multilayer circuit board.